Spacer integration scheme in MRAM technology

ABSTRACT

A magneto resistive memory device is fabricated by etching a blanket metal stack comprised of a buffer layer, pinned magnetic layer, a tunnel barrier layer and a free magnetic layer. The problem of junction shorting from resputtered metal during the etching process is eliminated by formation of a protective spacer covering the side of the freelayer and tunnel barrier interface. The spacer is formed following the first etch through the free layer which stops on the barrier layer. After spacer formation a second etch is made to isolate the device. The patterning of the device tunnel junction is made using a disposable mandrel method that enables a self-aligned contact to be made following the completion of the device patterning process.

TECHNICAL FIELD

The field of the invention is that of magnetic random access memory(MRAM), in particular the design of an array device to improve thefabrication process yield.

BACKGROUND OF THE INVENTION

Magneto resistive tunnel junction devices used in a random access memoryarray are formed by depositing a blanket metal stack comprised of apinned magnetic layer, a tunnel barrier layer and a free magnetic layer,such as that described in U.S. Pat. No. 5,650,958. Several process stepsare made to define the magneto resistive tunnel junction device thatcomprises the storage element of a memory array cell. The bit is writtenby orienting the net magnetic moment of the free layer parallel orantiparallel to the pinned layer magnetic moment. The bit is read bysensing the amount of current tunneling through the barrier junctionfrom the free layer to the pinned layer. The two bit states correspondto the junction resistance of the parallel and antiparallel orientationsof the freelayer relative to the pinned layer.

In practice, the operation of the tunnel barrier device is morecomplicated than the simple model described above. In a product array ofmagneto resistive tunnel barrier devices, variations in the orientationof the freelayer magnetic moment, in nominally the same state, introduceadditional noise that the sense amplifiers must discern. Defectsgenerated in the sidewalls during the fabrication process can impart thetendency of the magnetic domains to orient in offaxis orientations. Thereduction of these variations by process improvements is desirable asthis results in larger signal margins in a product array. Additionalperformance is obtained by increasing the signal margin.

Workers in the field are aware that during the reactive ion etching (ordry etching) process of patterning the stack, the reactive ions causeexposed metal to sputter. Some of the sputtered material lands on theexposed sides of the upper layers of the etched stack. Metal depositedacross the tunnel barrier can cause an excessive leakage or shunt pathalong the exposed vertical etched surface that forms the sidewall of thestorage device. This can result in a defective bit in the memory storagearray. This problem is more pronounced for the cross point memoryarchitecture, in which the interconnect metal, usually copper, isexposed during the device etch increasing the probability for shortingthe junction.

SUMMARY OF THE INVENTION

The invention relates to a method for fabricating a magneto-resistivetunnel junction device for use in a memory cell, in which a set ofsidewalls protects exposed edges of sensitive layers during etching.

A feature of the invention is the passivation of the external edges ofexposed ferromagnetic layers.

Another feature of the invention is the formation of sidewalls along theedges of a temporary mandrel that supports the sidewalls and provides acontact into the cell.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1-8 show in partially pictorial, partially schematic form, crosssections of portions of a magneto resistive tunnel junction device,illustrating the process sequence made to define the invention describedherein.

DETAILED DESCRIPTION

Referring to FIG. 1, there is shown in cross section a portion of anintegrated circuit that is being prepared for construction of an MRAMcell, part of a memory array. Substrate 10, illustratively silicon, hasbeen prepared by forming wells, threshold implants, etc. as part ofstandard integrated circuit processing up to at least the first level ofinterconnect dielectric deposition.

In the portion illustrated here, conductive interconnection members 20and 22 have been formed in substrate 10 by damascene processing. To formthe next wiring layer, a dielectric layer, e.g. oxide 30 has been putdown and a via 44 and local device wiring interconnect 42 have beenformed. Illustratively, they are TaN, but any other conductive materialcompatible with standard processing, e.g. copper, tungsten or aluminum,could be used. The top surface of the local device wiring interconnect42 has been planarized by chemical-mechanical polishing (CMP) as isstandard in the field. This surface is critical to optimal MRAM deviceperformance and care must be made to mitigate surface roughness.

A blanket stack of magnetic material, denoted generally by the numeral100, has been deposited to form the basis for the array of MRAM devices.Stack 100 shows the generic three layers of a magnetic memory cell thepinned layer (110), the tunnel barrier layer (115) and the free layer(120). Each of these layers may be a composite of several sublayers, asshown in U.S. Pat. No. 5,650,958, assigned to the assignee hereof. Forexample, as shown in FIG. 2B, layer 110 in the Figures representsschematically the ferromagnetic pinned layer of the cell, plusadditional layers such as a buffer layer 101 on the bottom of layer 110(e.g. TaN), and a pinning layer 105 (e.g. PtMn or IrMn,) placed betweenthe buffer layer and the pinned layer, as well as the ferromagneticpinned layer 110 of CoFe. In the middle of the device, a dielectrictunnel barrier layer 115 (e.g. alumina) separates the two magneticconductive layers. At the top of the device, the free layer (e.g. NiFepermalloy, TaN or bilayer Ta/TaN) 120 may also include a cap layer 125.Free layer 120 may be, for example, a layer of permalloy (NiFe). Thetunnel barrier layer 115 is usually alumina (Al2O3) but any othermaterial providing tunnel barrier characteristics may also be used. Thepinned layer 110 may be a single layer of CoFe or a composite of CoFe/Rulayers, for example. Other ferromagnetic materials may be used in placeof those described herein to perform the same device function. Forexample, other alloy compositions of CoFe are employed as pinnedferromagnetic layers and also alloys of CoFe alloyed with B, Si, forexample are used for the freelayer 120.

In the course of fabricating a magneto resistive tunnel junction deviceto form a random access memory cell, a layer of appropriate magneticmaterials is etched to define sections of appropriate dimension. Thetunnel junction of the device is defined by etching the free magneticlayer and stopping on the tunnel barrier layer. Following the formationof the tunnel junction, a protective spacer covering the edges of thefree layer and tunnel barrier interface is fabricated before a secondetch is made to either isolate the devices or to etch through the pinnedmagnetic layer beneath the junction. In this case the second etchprocess is self-aligned to the first, which improves the symmetry of themagnetic flux that couples the softlayer to the hard or pinned layer onthe bottom interface of the tunnel barrier. This improves the electricalswitching characteristics of the device.

An advantageous feature of the invention is a temporary mandrel thatenables the formation of a self-aligned vertical electrode for contactto the free layer of the device. The disposable mandrel is used tosupport an etch mask in the form of a spacer along the sidewall of themandrel and the etched freelayer to the tunnel barrier interface. Anadvantage of this method is that the height if the mandrel can besubstantial, which allows the formation of a sufficient etch mask with athin sidewall. This feature is not required, however, for the sidewallspacer formation and a more traditional approach using a conductivehardmask, such as TiN or TaN, can also be used.

Another advantage of the invention is the formation of a passivationlayer, which reduces pinning of magnetic domains in the free layer fromimperfections in the device sidewall. Ideally, this reduction of pinningallows the freelayer to switch into two distinct predefined statesthereby providing improved signal-to-noise conditions for the arraysense amplifier. It is necessary for such signal improvement that thematerial surrounding the mandrel be deposited directly onto the exposedsurface of the junction which is the case for spacer depositionaccording to the invention. Utilizing the sidewall spacer to providejunction passivation permits this additional requirement to be satisfiedindependent of the choice of interlevel dielectric material, e.g.alumina or nitride.

The junction protection provided by the sidewall spacer of the inventionis particularly useful for the formation of a cross point memory arraydirectly on copper wiring. This cell architecture requires thefabrication of the magneto-resistive device directly on the interconnectwiring beneath the device. The fabrication of this device requiresetching completely through the magnetic metal stack, thereby exposingthe copper metal interconnect. The sputter yield of copper is relativelylarge, which increases the rate of redeposited metal during etch therebyincreasing the probability of junction shorting. By providing adielectric spacer along the sidewall of the tunnel junction, thepotential for sidewall shorting is substantially reduced.

As those skilled in the art are aware, the bit stored in the cell isread by flowing current through the tunnel barrier of the device from acontact shown in later figures through stack 100 and then throughinterconnections 42, 44 and 20. The bit is written by flowing a currenthorizontally in the figure through adjacent interconnect wiring belowand above the device, e.g. wiring interconnect 22 and one of the layersin the stack, also as is conventional for the magneto resistive devicedesign illustrated in the figures. The so-called offset cellarchitecture features a magneto resistive device wired in series with atransistor to provide increased signal and faster access time. Thecrosspoint device design wires the magneto resistive device betweenadjacent wiring levels in an integrated circuit which results in acommon bottom contact for the read and write operations.

Referring to FIG. 3, an illustrative cell in the array is patterned byfirst forming a mandrel 60 on the stack of magnetic materials, themandrel comprising a spinon glass 61 (SOG,) a dielectric mask bottomlayer of nitride 62 and an upper layer of oxide 64. Alternative hardmaskmaterials, such as TiN or TaN, may similarly be used in the patterningprocess, as those skilled in the art are aware. In the manufacturingsequence, the mandrel hardmask 60 for the subsequent metal etch processis formed and the magnetic layers are etched using the mandrel as amask. The ferromagnetic freelayer 120 is etched, stopping on the tunnellayer 115 to define cell layers 122 and 117, respectively, shown in FIG.3. Alternatively, the freelayer etch process could etch through thetunnel barrier layer 115 and pinned layer 110 stopping on or in thepinning layer that is a lower level in the composite layer 110.

Illustratively, the etch proceeds through TaN cap layer 125 andfreelayer 120 and stops on the barrier layer 115, using, for example, achlorine-based reactive etch chemistry masked by the mandrel structure60 or alternative conductive hardmask. Another option would employ asimilar etch chemistry to etch the freelayer 120, barrier layer 115 andpinned layer 110, stopping on or in the pinning layer 105 that is thenext level in the composite layer 110. The etch chamber processconditions are adjusted together with plasma emission spectroscopymeasurements to facilitate an endpoint signal for an etch stop on theparticular layer. The freelayer 120 and barrier layer 115 are aboutforty and ten Angstroms thick, respectively, requiring etch selectivitycontrol to achieve the stop on the barrier in addition to the previousprocess controls. The result is shown in FIG. 3, with the upper layersof the magnetic stack patterned.

An important problem addressed by the invention is that of currentleakage along these stack edges and also direct shorting of the barrierlayer 115, which are caused in prior art fabrication by sputtering ofmetal from the pinned layer 110 or pinning layer. The sidewallredeposition is more of a problem with the crosspoint device structuresince copper, which has a high sputter yield, is exposed during themetal stack etch.

With the hardmask mandrel 60 and tunnel barrier of the magneto resistivedevice patterned, as illustrated in FIG. 3, a blanket dielectric layer72 such as SiN, Al2O3, or other material that can be deposited at atemperature compatible with back end processing and can be removed witha directional etch, is conformally deposited on the wafer as shown inFIG. 4. The properties of the material are designed to minimize theleakage current along the device sidewalls, in addition to optimizingdevice characteristics such as reliability. This layer is then etchedwith a suitable fluorine-based dielectric etch chemistry available incommercial etch tooling to form the passivation sidewall spacer 82 shownin FIG. 5. After the sidewall formation, layer 110 is etched outside thesidewall spacer 82, leaving the structure shown in FIG. 6, with the cellstack having sidewall spacer 82 that rests on horizontal projections oflayer 112, formed from the composite pinned layer.

Advantageously, the stack material at the edges of the free and tunnellayers is passivated by dielectric 72 and/or the material of sidewalls82. Any sputtering from the exposed surfaces of pinned ferromagneticlayer 110, the pinning layer 105, the buffer layer 101, or metal 42 willnot deposit on the exposed edges of layers 122 and 117 because of theprotective effect of sidewalls 82.

The mandrel hardmask structure 60 with the sidewall spacer 82 formedaround the perimeter of the device, illustrated in FIG. 6, is then usedto complete the metal etch process for the particular device. For theoffset device illustrated herein, the additional etch process involvesetching through pinned layer 110 stopping on or in the pinning layer.This results in formation of the shaped layers 122, 117 and 112, shownalso in FIG. 6. It may also be desirable to etch through the pinninglayer 105, stopping on the TaN buffer layer 101 at the bottom ofcomposite layer 110. Another option is to etch through the pinned layer110, the pinning layer 105 and the TaN buffer layer 101. This lastmethod is preferably used to pattern the crosspoint device or the offsetdevice using a damascene wiring strap 42 illustrated in FIG. 1. Thewiring strap is formed prior to deposition of magnetic layer 100. Any ofthese options can be used for the offset device structure withappropriate modifications to the device structure. Following patterningof the device junction, the offset cell might require, depending on theetch option chosen from the previous paragraph, an additionallithography and metal etch step for the formation of the local wiringstrap.

Referring now to FIG. 6, a relatively thick dielectric layer 86 isdeposited over the entire structure, including the space between cells,to a depth sufficient to allow for formation of a contact. Excessamounts of layer 86 are removed to expose the top surface of mandrel 60.The mandrel is removed in a conventional dielectric etch, leaving anaperture 66 having layer 122 (the top layer of the magnetic stack 100)on its bottom, that will be filled with an electrode for the cell.Illustratively, the etch is made using a oxygen based plasma stripprocess, with substantial selectivity to the cap layer material 122. Asshown in FIG. 7, a layer of copper is deposited to form electrode 92.

Illustratively, final dielectric 86 is SiLK(TM) or other low-k materialfor a high-performance integrated circuit. Other conventional interlayerdielectric materials could be used, as well, especially if highswitching speed is not required in the particular application.

A final structure is shown in FIG. 8, in which a second metal layer 95has been deposited and planarized, making contact with electrode 92.Those skilled in the art will be aware that the connections for thewrite currents for the cell have been omitted from these cross sections,(illustratively they extend perpendicular to the plane of the drawing),for clarity in presentation.

Those skilled in the art will be aware that many different combinationsof materials may be used, so long as they are compatible with theetching material and other requirements. The substrate may be SiGe, GaAsor any other semiconductor. The cell has been shown as resting on thesubstrate, but may be formed at a higher level in the total integratedcircuit structure. The structure of having the pinned layer on thebottom may be reversed with the free layer on the bottom and the pinnedlayer on the top. The electrical connections are preferably copper in alow-k dielectric, but may be aluminum in oxide or any other combinationmeeting the electrical requirements of the chip being fabricated. Thechip may be a magnetic random access memory or may be a logic chipcontaining an array of memory cells in it.

While the invention has been described in terms of a single preferredembodiment, those skilled in the art will recognize that the inventioncan be practiced in various versions within the spirit and scope of thefollowing claims.

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 10. (canceled) 11.A magnetic memory cell comprising a free layer, a pinned layer and atunnel barrier layer disposed on a vertical axis between said free layerand said pinned layer; a lower cell electrode disposed verticallybeneath said pinned layer and in electrical contact therewith; an uppercell electrode disposed vertically over said free layer and inelectrical contact therewith; a set of dielectric sidewalls enclosingsaid cell electrode and extending substantially vertically along atleast an exposed edge of said free layer, said dielectric sidewallsbeing disposed substantially vertically above an extension of saidpinned layer that extends horizontally past said free layer.
 12. Amagnetic memory cell according to claim 11, in which said dielectricsidewalls are formed from a passivation material, whereby saiddielectric sidewalls passivate said exposed edge of said free layer. 13.A magnetic memory cell according to claim 11, in which said dielectricsidewalls extend vertically through a pinning layer that is a sublayerof said pinned layer, whereby said pinning layer has an exposed edgevertically aligned with said exposed edge of said free layer.
 14. Amagnetic memory cell according to claim 13, in which said dielectricsidewalls are formed from a passivation material, whereby saiddielectric sidewalls passivate said exposed edge of said free layer. 15.A magnetic memory according to claim 11, in which said dielectricsidewalls are self-aligned with said extension of said pinned layer,whereby said dielectric sidewalls and said pinned layer havesubstantially vertical outer edges that are vertically aligned.
 16. Amagnetic memory according to claim 12, in which said dielectricsidewalls are self-aligned with said extension of said pinned layer,whereby said dielectric sidewalls and said pinned layer havesubstantially vertical outer edges that are vertically aligned.
 17. Amagnetic memory according to claim 13, in which said dielectricsidewalls are self-aligned with said extension of said pinned layer,whereby said dielectric sidewalls and said pinned layer havesubstantially vertical outer edges that are vertically aligned.
 18. Amagnetic memory according to claim 14, in which said dielectricsidewalls are self-aligned with said extension of said pinned layer,whereby said dielectric sidewalls and said pinned layer havesubstantially vertical outer edges that are vertically aligned.